`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:09:43 08/12/2015 
// Design Name: 
// Module Name:    MainUart 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module MainUart
     #( // Default setting:
      // 19,200 baud, 8 data bits, 1 stop bit, 2^2 FIFO
      parameter DBIT = 8,     // # data bits
                SB_TICK = 16, // # ticks for stop bits, 16/24/32
                              // for 1/1.5/2 stop bits
                DVSR = 325,   // baud rate divisor
                              // DVSR = 50M/(16*baud rate)
                DVSR_BIT = 9, // # bits of DVSR
                FIFO_W = 1 )   // # addr bits of FIFO
                              // # words in FIFO=2^FIFO_W
   
   (input clk, reset,
    input rx,
    output wire tx,
	 //output wire [7:0] salida,
	 //output wire done,
	 output wire run_pipe,
	 output wire [6:0] estado,
	 output wire [7:0] entrada_tx
	 );

   // signal declaration
   wire tick;
	wire tx_done;
	wire tx_start;
	wire rx_done;
	wire [7:0] data_rx_out;
	wire [7:0] data_tx_in;
	wire [7:0] contador;
	wire senal_cont;
	wire reset_cont;
   //body
	
	//assign salida = data_rx_out;
	//assign done = rx_done;
	assign entrada_tx = data_tx_in;
	
   mod_m_counter #(.M(DVSR), .N(DVSR_BIT)) baud_gen_unit
      (.clk(clk), .reset(reset), .q(), .max_tick(tick));

  uart_rx #(.DBIT(DBIT), .SB_TICK(SB_TICK)) uart_rx_unit
      (.clk(clk), .reset(reset), .rx(rx), .s_tick(tick),
       .rx_done_tick(rx_done), .dout(data_rx_out));
  
	uart_tx #(.DBIT(DBIT), .SB_TICK(SB_TICK)) uart_tx_unit
      (.clk(clk), .reset(reset), .tx_start(tx_start),
       .s_tick(tick), .din(data_tx_in),
       .tx_done_tick(tx_done), .tx(tx));

	DebugUnit debug(.clk(clk),
	.reset(reset),
	.rx_out(data_rx_out),
	.rx_done(rx_done),
	.tx_done(tx_done),
	.tx_in(data_tx_in),
	.tx_start(tx_start),
	.run_pipe(run_pipe),
	.estado(estado),
	.cont(contador),
	.Scont(senal_cont),
	.Rcont(reset_cont)
	);
		 
	Contador Cuenta(
	.clk(clk),
	.reset(reset_cont),
	.contadorOut(contador),
	.contadorIn(contador),
	.senal(senal_cont));

endmodule

